For memories such as static random access memories (RAM) and multi-port memories of the type in which high speed data accesses are carried out sequentially at high speed cycle time, it is necessary to execute a series of data reading operations as fast as possible. A series of data reading operations by such memories includes the following operations. Namely, memory cells or data registers are selected. The data read therefrom are outputted to a common data bus pair (DQ line pair) and amplified by sense amplifiers at several stages to MOS logic levels. The amplified data are supplied to a common data output buffer and outputted to an external output pin as a "0" level data or a "1" level data. Such a series of operations is required to be carried out at high speed.
FIG. 1 is a block diagram showing a semiconductor integrated circuit according to a background art. As shown in FIG. 1, complementary data read from data storage means M such as a memory cell are outputted onto a pair of data busses DQ and DQ (DQ line pair). The data on the DQ line pair are amplified by a sense amplifier A to a power supply potential level V.sub.CC and to a ground potential level V.sub.SS, respectively, and outputted onto a RD line pair of RD and RD. In accordance with a pair of data on the RD line pair, a "1" level signal or a "0" level signal is outputted to an external output pin I/O via a data output buffer C.
In FIG. 1, Te1 and Te2 represent equalizing transistors which equalize the DQ line pair and RD line pair, respectively.
The circuit constructed as above operates in the manner shown in the timing chart of FIG. 2. In FIG. 2, FIG. 2(A) shows a cycle signal SC which indicates a data read cycle for reading a data from a memory, FIG. 2(B) shows a signal on the DQ line pair inputted to the sense amplifier A, FIG. 2(C) shows a signal on the RD line pair inputted from the sense amplifier A to the data output buffer C, and FIG. 2(D) shows a signal outputted from the data output buffer C to the external output pin I/O.
The data read from a memory cell or the like appear at the DQ line pair at time t1. The read-out data are supplied to and amplified by the sense amplifier A to the power supply potential level V.sub.CC and to a ground potential level V.sub.SS, i.e., to MOS logic levels. Thereafter, at time t2 the amplified signals are outputted from the sense amplifier A onto the RD line pair. In response to a change of the cycle signal SC at time t3, the data output buffer C latches the data on the RD line pair at time t4 and outputs the data to the external output pin I/O.
The above operations are repeated to sequentially read data from different memory cells. After the data from a memory cell or the like (data on the RD line pair) are loaded in the data output buffer C, the DQ line pair and RD line pair are equalized at time t5 before the next data are read from a memory cell.
The semiconductor integrated circuit according to the background art operates in the above-described manner. It is therefore possible to read information in a memory cell or data register and output the information onto the DQ line pair at high speed. However, the sense amplifier A must continue to latch the data on the RD line pair while the data on the RD line are being transferred to the data output buffer C.
As described above, after the data on the RD line pair were loaded in the data output buffer C, the DQ line pair and RD line pair are equalized and thereafter, the data on the DQ line pair for the next cycle are sensed and amplified by the sense amplifier A and outputted onto the RD line pair. In this case, however, as the cycle time becomes shorter, it becomes difficult to complete the equalization of the DQ line pair before the next cycle data are read, resulting in a residual hysteresis which causes a high possibility of a read error at the next cycle.
Particularly in the case where an access address for the next cycle has been already determined as in the case of a serial port of a multi-port memory, high speed data access and high speed cycle time depend on the time from the start of data latch on the RD line pair by the sense amplifier to the end of equalizing the DQ line pair.
In order to realize high speed data access and high speed cycle time of the operation of the circuit according to the background art, the amplitudes of signals on the RD line pair may be made large. To this end, it becomes necessary to make the driving power of the sense amplifier A large. Accordingly, power consumption increases, and moreover a logic level inputted from the external is likely to be detected erroneously because of power source noises.